OK3588J-UP5 Single Board Computer
CPU: Rockchip RK3588/RK3588J
Architecture: 4x Cortex-A76+4x Cortex-A55
Frequency: [email protected]/1.6GHz, [email protected]/1.3GHz
RAM: 4GB/8GB/16GB/32GB LPDDR4
ROM: 32GB/64GB/128GB eMMC
System: Android14，ForlinxDesktop 24.04，Linux 6.1
OK3588J-UP5 Development Board | Rockchip RK3588 Industrial Evaluation Kit
The OK3588J-UP5 Development Board/Single Board Computer combines the industrial-grade FET3588J-UP5 SoM with an expansion carrier board to deliver a production-ready evaluation platform. Engineered with rich high-speed interfaces—including 8K HDMI output, quad-channel MIPI CSI, PCIe 3.0, and 5G/Wi-Fi 6 expansion—it eliminates baseboard design complexities and accelerates proof-of-concept transitions into mass deployment across edge AI, smart vision, and industrial computing applications.
▊ Hardware Features
| Hardware Parameters of FET3588J-UP5 | ||
|---|---|---|
| Processor | Rockchip RK3588/RK3588J | |
| RK3588 CPU：4×[email protected] + 4×[email protected] | ||
| RK3588J CPU：4×[email protected] + 4×[email protected] | ||
| NPU | 6 TOPS, supporting INT4/INT8/INT16/FP16 combined operations | |
| GPU | Mali-G610 MP4, OpenGLES 1.1, 2.0, 3.2, OpenCL 2.2, Vulkan1.2 | |
| VPU |
Hardware Decoding: • H.265, VP9: up to 8K@60fps • H.264: up to 8K@30fps • AV1: up to 4K@60fps |
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Hardware Encoding: • H.265/HEVC, H.264/AVC: up to 8K@30fps |
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| RAM | 4GB/8GB/16GB/32GB LPDDR4 | |
| ROM | 32GB/64GB/128GB eMMC | |
| Operating Voltage | DC 5V-13V | |
| Operating Temperature | 0℃ ~ +70℃ / -40℃ ~ +85℃ | |
| Net Weight | 15.9g | |
| Connection | LGA (624 pins; the ball pitch of the LGA is 1.25 mm, and the diameter of a single ball is 0.8 mm) | |
| SoM Function Parameters of FET3588J-UP5 | ||||
|---|---|---|---|---|
| Function | Maximum Number | Parameter | Number of interfaces defined by UP5 | Parameter |
| MIPI DC PHY (DPHY/CPHY) *1 | 2 | Supports DPHY or CPHY; 4-channel MIPI DPHY V1.2, up to 2.5 Gbps per lane; 3-channel MIPI CPHY V1.1, up to 2.5 Gbps per lane; | \ | |
| MIPI CSI DPHY*1 | 4 | 2-channel MIPI DPHY V1.2, with a maximum data rate of 2.5 Gbps per lane; every two 2-channel DPHYs can be combined to form a single 4-channel DPHY for a parallel display interface, supporting a maximum resolution of WUXGA (1920 x 1200 @ 60 fps, 165 MHz pixel clock) | 4 | 1 x 4-channel MIPI DPHY V2.0, with a maximum of 4.5 Gbps per lane; 3 x 2-channel MIPI DPHY V1.2, with a maximum of 2.5 Gbps per lane; any two 2-channel DPHYs can be combined into a single 4-channel DPHY to serve a parallel display interface, supporting a maximum resolution of WUXGA (1920 x 1200 @ 60 fps, 165 MHz pixel clock) |
| DVP | 1 | 8/10/12/16-bit standard DVP interface, with a maximum data input rate of 150 MHz; supports BT.601/BT.656 and BT.1120 VI interfaces; | \ | |
| HDMI RX | 1 | Supports HDMI 2.0 at 3.4 Gbps to 6 Gbps; supports HDMI 1.4b at 250 Mbps to 3.4 Gbps; supports HDCP 2.3 and HDCP 1.4; | 1 | Supports HDMI 2.0 at 3.4 Gbps to 6 Gbps; supports HDMI 1.4b at 250 Mbps to 3.4 Gbps; supports HDCP 2.3 and HDCP 1.4; |
| HDMI/eDP TX | ≤2 | Supports 2 x HDMI/eDP TX combination ports (HDMI and eDP cannot operate simultaneously), with each port supporting x1, x2 and x4 configurations; HDMI supports a resolution of 7680x4320@60Hz, with bandwidths of 3, 6, 8, 10 and 12 Gbps, and supports HDCP 2.3; eDP supports a resolution of 4K@60Hz, with bandwidths of 1.62 Gbps, 2.7 Gbps and 5.4 Gbps, and supports HDCP 1.3; | 2 | Supports 2 x HDMI/eDP TX combination ports (HDMI and eDP cannot operate simultaneously), with each port supporting x1, x2 and x4 configurations; HDMI supports a resolution of 7680x4320@60Hz, with bandwidths of 3, 6, 8, 10 and 12 Gbps, and supports HDCP 2.3; eDP supports a resolution of 4K@60Hz, with bandwidths of 1.62 Gbps, 2.7 Gbps and 5.4 Gbps, and supports HDCP 1.3; |
| DP TX | 2 | Supports 2 x DP TX 1.4a ports, compatible with USB 3.1 Gen 1, supporting 1, 2 or 4 channels; resolution up to 7680x4320@30Hz; supports DP Alt Mode via USB Type-C; | \ | |
| MIPI DSI | 2 | Supports 2 x MIPI DPHY 2.0 or CPHY 1.1 interfaces, with a resolution of up to 4K@60Hz; supports dual MIPI displays in left-right mode, and supports RGB/YUV formats (up to 10-bit); | 2 | Supports 2 x MIPI DPHY 2.0 or CPHY 1.1 interfaces, capable of achieving up to 4K@60Hz resolution. It also supports dual MIPI display in left-right mode and supports RGB/YUV formats (up to 10-bit). |
| BT.1120 output | 1 | Supports RGB format (up to 8-bit), with a data rate of up to 150 MHz; resolution up to 1920x1080@60Hz; | \ | |
| I2S | ≤4 | Transmits and receives clock signals up to 50 MHz; supports time-division multiplexing (TDM), Inter-IC Communication (I2C) and similar formats; supports digital audio interface transmission (SPDIF, IEC 60958-1 and AES-3 formats); supports audio reference output clock; | 1 | Transmits and receives clock signals up to 50 MHz; supports time-division multiplexing (TDM), Inter-IC Communication (I2C) and similar formats; supports digital audio interface transmission (SPDIF, IEC 60958-1 and AES-3 formats); Supports an audio reference output clock; |
| SPDIF | 2 | Supports storage of 2x 16-bit audio data; Supports dual-phase stereo output; | \ | |
| PDM | 2 | Up to 8 channels, with audio resolution ranging from 16 to 24 bits and a sampling rate of up to 192 kHz; supports PDM master receiver mode; | \ | |
| DSM PWM | 1 | The audio PCM data is converted via direct bitstream digital encoding to produce a 1-bit signal stream; the output digital signal can be filtered to produce an audio signal; | \ | |
| Ethernet | 2 | 2 x GMAC, providing RGMII / RMII interface pins; supports 10/100/1000 Mbps data transfer rates; | 2 |
2 × GMAC with RGMII / RMII interfaces Supports Data rates: 10/100/1000 Mbps； |
| USB3.1 Gen1*2 | 3 | USB 3.1 Gen 1 data transfer rates of up to 5 Gbps; 2 x USB 3.1 OTG, shared with DP TX (USB3OTG_0 and USB3OTG_1); USB3OTG_0 and USB3OTG_1 support USB Type-C and DP Alt; 1 x USB 3.1 Host, shared with PIPE PHY2 (USB3OTG_2); | 3 | USB 3.1 Gen 1 data transfer rates of up to 5 Gbps; 2 x USB 3.1 OTG ports, USB3OTG_0 and USB3OTG_1, which support USB Type-C; 1 USB 3.1 Host port; |
| USB 2.0 Host | 2 | Supports 2 x USB2.0 Host； | \ | |
| PCIe 2.0*2 | ≤3 | Each PCIe2.1 interface supports 1 lane, with data rate up to 5Gbps; | ≤2 | Each PCIe2.1 interface supports 1 lane, with data rate up to 5Gbps; |
| PCIe 3.0*2 | ≤4 | Supports RC and EP, with a maximum data rate of 8 Gbps; supports four configuration options: 1 x 4, 2 x 2, 4 x 1, and 1 x 2 + 2 x 1; | 2 | Supports RC and EP, with a maximum data rate of 8 Gbps; supports four configuration options: 1 x x4, 2 x x2; |
| SDMMC | 1 | Integrated with 1 SDMMC controller and 1 SDIO controller, both supporting the SDIO 3.0 protocol and MMC V4.51 protocol. | 1 | Integrated with 1 SDMMC controller and 1 SDIO controller, both supporting the SDIO 3.0 protocol and MMC V4.51 protocol. |
| SDIO | 1 | 1 | ||
| SPI | ≤5 | Each controller supports two chip-select outputs; it supports both serial master and serial slave modes, which are software-configurable; | 2 | Each controller supports two chip-select outputs; it supports both serial master and serial slave modes, which are software-configurable; |
| I2C | ≤9 | Supports 7-bit and 10-bit address modes; data transfer rates of up to 100 kbits/s in standard mode and up to 400 kbits/s in high-speed mode; | 4 | Supports 7-bit and 10-bit addressing modes; standard mode data rate up to 100k bits/s, fast mode up to 400k bits/s. |
| UART | ≤10 | Features two built-in 64-bit FIFOs, which can be used separately for TX and RX; supports 5-bit, 6-bit, 7-bit and 8-bit serial data transmission and reception, with baud rates up to 4 Mbps; all 10 UARTs support automatic flow control mode; | 4 | Features two built-in 64-bit FIFOs, which can be used separately for TX and RX; supports 5-bit, 6-bit, 7-bit and 8-bit serial data transmission and reception, with baud rates up to 4 Mbps; all UARTs support automatic flow control mode; two of them support 485; |
| SATA*2 | ≤3 | Features three SATA 3.0 controllers, and the PCIe and USB 3.0 HOST 2 controllers share PIPE PHY 0/1/2; supports eSATA, with a maximum data rate of 6 Gbps; | \ | |
| PWM | ≤16 | Supports up to 16 on-chip PWM with interrupt-based operation and capture mode; | 2 | Features interrupt-based operation and supports capture mode. |
| ADC | ≤8 | Supports 8 x 12bit single-ended input SAR-ADC with sampling rate up to 1MS/s; | 7 | Supports 8 x 12bit single-ended input SAR-ADC with sampling rate up to 1MS/s; |
Note*: The maximum number of parameters in the table is the theoretical value of hardware design or CPU; The number of interface resources defined by UP5 in the table is the maximum number supported by the UP5 universal package.
▊ RK3588 UP5 Carrier Board
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| Development Board Function Parameters | ||
|---|---|---|
| Function | Quantity | Parameter |
| MIPI CSI | 4 | 1 x MIPI DPHY V2.0 4-lane interface, supporting up to 4.5 Gbps per lane; connected via a 26-pin FPC socket, with the OV13850 camera mounted by default; 3 x MIPI DPHY V1.2 2-lane interfaces, supporting up to 2.5 Gbps per lane; brought out via three 26-pin FPC sockets; pre-mounted with an OV5645 camera by default; |
| MIPI DSI | 2 | Each MIPI interface supports 4 lanes of output, with a maximum resolution of 4K@60fps; compatible with Feiling’s 7-inch MIPI display, with a resolution of 1024 x 600@30fps; supports separate display and touch functionality. |
| HDMI RX | 1 | Led out via a standard HDMI connector; supports up to 4K@60Hz. |
| HDMI TX | 1 | Led out via a standard HDMI connector; supports up to 7680x4320@60Hz. |
| eDP TX | 1 | Compatible with 1080p@60Hz displays; supports up to 4K@60Hz. |
| USB3.1 Gen1 | 2 |
Led out via the Type-C interface; Used in conjunction with DP TX, with data rates of up to 5 Gbps; |
| USB3.0 Host | 1 | Connected via a Type-A USB port, with transfer speeds of up to 5 Gbps; |
| USB2.0 Host | 1 | Led out via a Type-A USB interface; supports High-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) modes. |
| PCIe3.0 | 2 | 2x2-lane PCIe signals routed out via two PCIe x4 slots; supports data rates of 2.5 Gbps (PCIe 1.1), 5 Gbps (PCIe 2.1) and 8 Gbps (PCIe 3.0); |
| PCIe2.0 | 2 | Led out via one M.2 M-Key slot; supports speeds up to 5 Gbps |
| Ethernet | 2 |
Led out via 2 x RJ45 interfaces; Supports 10/100/1000 Mbps data transmission rate. |
| TF Card | 1 | TF card is available, rate up to 150MHz，support SDR104 mode; |
| Audio | 1 | Codec chip on board, support headphone output, MIC input level Speaker output and other functions; |
| RS485 | 2 | 2 x RS485 CAN bus routed out through RS485 transceiver; |
| CAN | 1 | Connect one CAN bus via the CANFD transceiver; |
| UART | 1 | Led out via 2.54 mm pitch;Up to 4Mbps baud rate; |
| 4G/5G | 1 | Supports M.2 packaged 4G/5G modules; |
| WIFI&BT | 1 | Supports Wi-Fi and Bluetooth modules in M.2 form factor; Forlinx has adapted modules that support Wi-Fi 6 SU and MU-MIMO, as well as Bluetooth 5.3; |
| ADC | 5 | Led out via a PH2.0 socket; 12-bit resolution and a sampling rate of up to 1 MS/s; |
| RTC | 1 | Onboard RTC chip and battery socket; |
| SPI | 2 | Routed via a 2.54mm pitch connector; |
| FAN | 1 | Onboard fan connector; |
Note*: The parameters in the table are the theoretical values of hardware design or CPU.
▊ Accessories
Please click here to get more information about the supported modules and accessories.
▊ Documentation
Reference Manuals
Hardware Related
Product Datasheet
User Guide
Carrier Board Schematic
Carrier Board PCB
SoM Pinmux
Software & BSP
OS Image
Testing Demo
Source Code
Manual
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▊ Forlinx Recommended Products
Architecture: 4x Cortex-A76+4x Cortex-A55
Frequency: [email protected]/1.6GHz, [email protected]/1.3GHz
RAM: 4GB/8GB/16GB/32GB LPDDR4
ROM: 32GB/64GB/128GB eMMC
Architecture: 4x Cortex-A72 + 4x Cortex-A53
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ROM: 16GB eMMC，32GB/64GB eMMC
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