With the rapid development of computer and network communication technology, the era of digitalization and networking of thermal automation system in thermal power plants has come. On the one hand, it provides a better platform for data exchange, analysis and application between control and information systems, on the other hand, it puts forward higher requirements for the accuracy of time labels of various real-time and historical data.

The use of inexpensive satellite clocks to unify the clocks of various systems throughout the plant is the standard practice used in the design of thermal power plants.

The main clock such as unit decentralized control system, auxiliary system programmable controller, plant-level monitoring information system, power plant management information system (MIS) and so on obtain the standard TOD time through the appropriate GPS clock signal interface, and then according to the respective clock synchronization mechanism, the clock deviation in the system is limited to a small enough range to achieve the clock synchronization of the whole plant.

First, the composition of the clock system

Clock synchronization systems have several forms, typical of which are two, as follows:

1, Single master clock synchronization system

Consisting of a master clock, multiple slave clocks, and signal transmission media, the master clock may have an interface to receive the wired time reference signal from the previous clock synchronization system, depending on actual needs and technical requirements, for timing equipment or system alignment.

2.Dual master clock synchronization system

It is composed of two master clocks, multiple slave clocks and signal transmission media to synchronize the time of the timed equipment or system. According to actual needs and technical requirements, the master clock can reserve an interface for receiving the wired time reference signal issued by the upper-level time synchronization system.

Second, the configuration of the clock synchronization system

1. Single master clock synchronization system

Beidou+GPS, suitable for small power plants, 35kV and below substations.

2. Dual master clock synchronization system

Double Beidou + Double GPS, suitable for all levels of control centers, large power plants, 110kV and above substations.

Third, the basic composition of the clock synchronization system

The clock synchronization device is mainly composed of three parts: the clock input unit, the internal clock unit and the time output unit.

The accuracy of the time signal and time information of the input device must not be lower than the accuracy requirements of the time signal and time information output of the device to ensure the proper operation of the time-granted equipment.

Fourth, the technical application of the localization program

The main control selection of Forlinx FETA40i-C core board

• Performance: Quad-core Cortex -A7, A40i design
• Power guarantee: dual power supply, mutual main preparation
• LCD: Display, human-computer interaction
• Key: Key on the front panel
• SPI: Pick up FPGAs and interact with FETA40i-C for information
• IIC: RTC chip
• Serial: CONNECT GPS module and Beidou module
• GPIO: Control interrupts
• Network Port: 2 lanes, do communication time

Platform benefits

FETA40i-C core board, based on the domestic Allwinner industry platform-level processor quad-core Cortex-A7 A40i design, main frequency 1.2GHz, integrated Mali-400MP2 GPU, memory 1GB/2GB DDR3L, storage 8GB eMMC. Supports most of the current popular video and picture format decoding, with stable and reliable industrial-grade product performance and cost-effective low power consumption and other advantages, equipped with Linux and Android operating systems.

Detailed parameters

• Allwinner industrial-grade A40i quad-core Cortex-A7, with a main frequency of up to 1.2GHz and an integrated Mali-400MP2 GPU;
• Support for dual-screen homage and multiple display interfaces RGB/MIPI /dual 8-bit LVDS /HDMI/TV OUT, 1920x1080@60fps;
• Support for 1 gigabit network, 100M network, support for WiFi/BT4.0, support for 4G;
• Support for multiple camera inputs, two DVP camera interfaces, up to 500W pixels, four TVNs, support for NTSC and PAL system;
• CPU internal integration Audio Codec, support 1 differential PHONEOUT, 1 stereo headphone output, 1 microphone input;
• The external expansion interface is rich in 8xUART, 4xSD, 3xUSB, 4xSPI, 5xIIC, SATA, 8xPWM, etc.