RK3588 has a very rich expansion interface, highly integrated SoC design, which can effectively reduce the cost of whole product.

Embedded 3D GPU ARM Mali G610 makes RK3588 completely compatible with OpenGLES 1.1, 2.0, and 3.2, OpenCL up to 2.2 and Vulkan1.2. Special 2D hardware engine with MMU will maximize display performance and provide very smoothly operation.

RK3588 introduces a new generation totally hardware-based maximum 48-Megapixel ISP (image signal processor). It implements a lot of algorithm accelerators, such as HDR, 3A, LSC, 3DNR, 2DNR, sharpening, dehaze, fisheye correction, gamma correction and so on.

The build-in NPU supports INT4/INT8/INT16/FP16 hybrid operation and computing power is up to 6TOPs. In addition, with its strong compatibility, network models based on a series of frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.

RK3588 has high-performance quad channel external memory interface (LPDDR4/LPDDR4X/LPDDR5) capable of sustaining demanding memory bandwidths, also provides a complete set of peripheral interface to support very flexible applications.

▊ Microprocessor

• Quad-core ARM Cortex-A76 MPCore processor and quad-core ARM Cortex-A55 MPCore processor, both are high-performance, low-power and cached application processor
• Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerating media and signal processing
• ARMv8 Cryptography Extensions
• Trustzone technology support
• Integrated 64KB L1 instruction cache, 64KB L1 data cache and 512KB L2 cache for each Cortex-A76
• Integrated 32KB L1 instruction cache, 32KB L1 data cache and 128KB L2 cache for each Cortex-A55
• Quad-core Cortex-A76 and Quad-core Cortex-A55 share 3MB L3 cache
• Eight separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario
• PD_CPU_0: 1st Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_1: 2nd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_2: 3rd Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_3: 4th Cortex-A55 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_4: 1st Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_5: 2nd Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_6: 3rd Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
• PD_CPU_7: 4th Cortex-A76 + Neon + FPU + L1/L2 I/D Cache
• Three isolated voltage domains to support DVFS, one for A76_0 and A76_1, one for A76_2 and A76_3, the other for DSU and Cortex-A55.

▊ Internal on-chip memory

BootRom spatial size : 32KB

Support system boot from the following device:

• SPI interface
• eMMC interface
• SD/MMC interface

▊ Dynamic Memory Interface

Compatible with JEDEC standards LPDDR4/LPDDR4X/LPDDR5

Support four channels, each channel 16bits data widths. Totally up to 32GB address space

▊ PMU(power management unit)

Multiple configurable work modes to save power by different frequency or automatic clock gating control or power domain on/off control

Lots of wakeup sources in different mode

Support 10 separate voltage domains

Support 45 separate power domains, which can be power up/down by software based on different application scenes

▊ Timer

Support 12 secure timers with 64bits counter and interrupt-based operation

Support 18 non-secure timers with 64bits counter and interrupt-based operation

Support two operation modes: free-running and user-defined count for each timer

Support timer work state checkable

▊ Watchdog

32-bit watchdog counter

Counter counts down from a preset value to 0 to indicate the occurrence of a timeout

▊ Secure System

Embedded two cipher engine

▊ Video CODEC

• Video Decoder
  Real-time video decoder of MPEG-1, MPEG-2, MPEG-4, H.263, H.264, H.265, VC-1, VP9, VP8, MVC, AV1
  MMU Embedded
  Multi-channel decoder in parallel for less resolution
  H.264 AVC/MVC Main10 L6.0 : 8K@30fps (7680x4320)
  VP9 Profile0/2 L6.1 : 8K@60fps (7680x4320)
  H.265 HEVC/MVC Main10 L6.1 : 8K@60fps (7680x4320)
  AVS2 Profile0/2 L10.2.6 : 8K@60fps (7680x4320)
  AV1 Main Profile 8/10bit L5.3 : 4K@60fps (3840x2160)
  MPEG-2 up to MP: 1080p@60fps ( 1920x1088)
  MPEG-1 up to MP: 1080p@60fps ( 1920x1088)
  VC-1up to AP level3: 1080p@60fps ( 1920x1088)
  VP8 version2: 1080p@60fps ( 1920x1088)
  
• Video Encoder
  Real-time H.265/H.264 video encoding
  Support up to 8K@30fps
  Multi-channel encoder in parallel for less resolution
  
• JPEG CODEC
  JPEG Encoder
  Baseline (DCT sequential)
  Encoder size is from 96x96 to 8192x8192(67Mpixels), up to 90 million pixels per second
  JPEG Decoder
  Decoder size is from 48x48 to 65536x65536
  Support YUV400/YUV411/YUV420/YUV422/YUV440/YUV444, up to 1080P@280fps, and 560 million pixels per second
  Support MJPEG
• Neural Process Unit
  Neural network acceleration engine with processing performance up to 6 TOPS
  Include triple NPU core, and support triple core co-work, dual core co-Work, and work independently. Embedded 384KBx3 internal buffer. Multi-task, multi-scenario in parallel.
  Support deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN, Android NN, etc.
• Graphics Engine
  3D Graphics Engine
  ARM Mali-G610 MP4
  High performance OpenGLES 1.1, 2.0 and 3.2, OpenCL 2.2, Vulkan1.2 etc.
  Support Serial Wire debug for embedded MCU
  One isolated voltage domain to support DVFS
• 2D Graphics Engine
  Source format: ARGB/RGB888/RGB565/YUV420/YUV422/BPP
  Destination formats: ARGB/RGB888/RGB565/YUV420/YUV422
  Max resolution: 8192x8192 source, 4096x4096 destination
  Arbitrary non-integer scaling ratio, from 1/8 to 8.
  0, 90, 180, 270 degree rotation, x-mirror, y-mirror&rotation operation

▊ Video Input Interface

• MIPI interface
  Two MIPI DC( DPHY/CPHY) combo PHY, support to use DPHY or CPHY
  Each MIPI DPHY V2.0, 4lanes, 4. 5Gbps per lane. Each MIPI CPHY V1.1, 3lanes, 2.5Gsps per lane
  Four MIPI CSI DPHY. Each MIPI DPHY V1.2, 2lanes, 2.5Gbps per lane.
  Support to combine 2 DPHY together to one 4lanes
  Support camera input combination:
  2 MIPI DCPHY + 4 MIPI CSI DPHY(2 lanes), totally support 6 cameras input
  2 MIPI DCPHY + 1 MIPI CSI DPHY(4 lanes) + 2 MIPI CSI DPHY(2 lanes), totally support 5 cameras input
  2 MIPI DCPHY + 2 MIPI CSI DPHY(4 lanes), totally support 4 cameras input
• DVP interface
  One 8/10/12/16-bit standard DVP interface, up to 150MHz input data
• BT interface
  Support BT.601/BT.656 and BT.1120 VI interface
  Support the polarity of pixel_clk, hsync, vsync configurable
• HDMI RX interface
  Support HDMI 2.0 RX, up to 4K@60fps video input
  Support HDCP2.3

▊ Image Signal Processor

• ViC(VICAP) input: RX RAW8/10/ 12
  Maximum input
  48M: 8064x6048@15 dual ISP
  32M: 6528x4898@30 dual ISP
  16M: 4672x3504@30 single ISP
• 3A: include AE/Histogram, AF, AWB statistics output
  FPN: Fixed Pattern Noise removal
  BLC: Black Level Correction
  DPCC: Static/Dynamic defect pixel cluster correction
  PDAF: Phase Detection Auto Focus
  LSC: Lens shading correction
  Bayer-2DNR: Spatial Bayer-raw De-noising
  Bayer- 3DNR: Temporal Bayer-raw De-noising
  CAC: Chromatic Aberration Correction
  HDR: 3-Frame Merge into High-Dynamic Range
  DRC: HDR Dynamic Range Compression, Tone mapping
  GIC: Green Imbalance Correction
  Debayer: Advanced Adaptive Demosaic with Chromatic Aberration Correction
  CCM/CSM: Color correction matrix; RGB2YUV etc
  Gamma: Gamma out correction
  Dehaze/Enhance: Automatic Dehaze and Effect enhancement
  3DLUT: 3D-Lut Color Palette for Customer
  LDCH: Lens-distortion only in the horizontal direction
  YUV-2DNR: Spatial YUV De-noising
  Sharp: Image Sharpening and boundary filtering
  CMSK: privacy mask
  GAIN: image local gain
  Support multi-sensor reuse ISP

▊ UI output

• HDMI/eDP TX interface
• Support two HDMI/eDP TX combo interface, but HDMI and eDP can not work at the same time for each interface
• DP TX interface, support 2 DP TX 1.4a interface which combo with USB3.1 Gen1
• MIPI DSI interface
• Support DSC 1.1/1.2a
• BT.1120 video output interface
• GVI, total 8 lanes, up to 4K@60hz, 3.75Gbps/lane

▊ Video Output Processor

• VOP0, maximum output resolution: 7680 x 4320 @ 60Hz
• VOP1, maximum output resolution: 4096 x 2304 @ 60Hz
• VOP2, maximum output resolution: 4096 x 2304 @ 60Hz
• VOP3, maximum output resolution: 1920 x 1080 @ 60Hz

▊ Audio Interface

• I2S0/I2S1 with 8 channels. Up to 8 channels TX and 8 channels RX path. Audio resolution from 16bits to 32bits. Sample rate up to 192KHz
• I2S2/I2S3 with 2 channels
• SPDIFO/SPDIF1
• PDMO/PDM1
• Up to 8 channels. Audio resolution from 16bits to 24bits. Sample rate up to 192KHz
• Support three modes of mixing for every digital DAC channel
  Support volume control
  VAD(Voice Activity Detection)
  Support read voice data from I2S/PDM
  Support voice amplitude detection
  Support Multi-Mic array data storing
  Support a level combined interrupt

▊ Connectivity

• SDIO interface. Compatible with SDIO3.0 protocol, 4-bit data bus widths
• GMAC 10/100/ 1000M Ethernet controller
  Support two Ethernet controllers
  Support 10/ 100/ 1000-Mbps data transfer rates with the RGMII interfaces
  Support 10/ 100-Mbps data transfer rates with the RMII interfaces
  Support both full-duplex and half-duplex operation
• USB3.1
  Universal Serial Bus 3.0 Specification, Revision 1.0
  Universal Serial Bus Specification, Revision 2.0
  eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.1
  Supports 5Gbps serializer/deserializer for USB
  Support USB Type-C and DP Alt Mode for 2 USB Gen1 combined with DP TX
• USB 2.0 OTG
  Universal Serial Bus Specification, Revision 2.0
  Extensible Host Controller Interface for Universal Serial Bus (xHCI), Rev. 1.1
  Support two USB 2.0 OTG
  Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) modes
  Support control/bulk/interrupt/isochronous transfer
  USB 2.0 OTG does not work with USB 3.1 at the same time
• USB 2.0 Host
  Compatible with USB 2.0 specification
  Support two USB 2.0 Host
  Supports high-speed( 480Mbps), full-speed( 12Mbps) and low-speed( 1.5Mbps) mode
  Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
  Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
• Support three Combo PIPE PHYs with PCIe2.1/SATA3.0/USB3.1 controller
  Combo PIPE PHY0 support one of the following interfaces
  SATA
  PCIe2.1
  Combo PIPE PHY1 support one of the following interfaces
  SATA
  PCIe2.1
  Combo PIPE PHY2 support one of the following interfaces
  SATA
  PCIe2.1
  USB3.0
  PCIe2.1 Interface:
  Compatible with PCI Express Base Specification Revision 2. 1
  Support 1 lane for each PCIe2.1 interface
  Support Root Complex(RC) only
  Support 5Gbps data rate
  SATA Interface
  Compatible with Serial ATA 3.1 and AHCI revision 1.3.1
  Support eSATA
  Support 1 port for each SATA interface
  Support 6Gbps data rate
• PCIe3.0 Interface :
  Compatible with PCI Express Base Specification Revision 3.0
  Support dual operation mode: Root Complex(RC) and End Point(EP)
  Support data rates: 2.5Gbps(PCIe1.1), 5Gbps( PCIe2.1), 8Gps(PCIe3.0)
  Support aggregation and bifurcation with 1x 4lanes, 2x 2lanes, 4x 1lanes and 1x 2lanes + 2x 1lanes
• SPI interface
  Support 5 SPI Controllers(SPI0-SPI4)
  Support two chip-select output
  Support serial-master and serial-slave mode, software-configurable
• I2C Master controller
  Support 9 I2C Master(I2C0-I2C8)
  Support 7bits and 10bits address mode
  Software programmable clock frequency
  Data on the I2C-bus can be transferred at rates of up to 100k bits/s in the Standard-mode, up to 400k bits/s in the Fast-mode
• UART interface
  Support 10 UART interfaces(UART0-UART9)
  Embedded two 64-byte FIFO for TX and RX operation respectively
  Support 5bit, 6bit, 7bit, 8bit serial data transmit or receive
  Standard asynchronous communication bits such as start, stop and parity
  Support different input clock for UART operation to get up to 4Mbps baud rate
  Support auto flow control mode for all UART
• GPIO
  All of GPIOs can be used to generate interrupt
  Support level trigger and edge trigger interrupt
  Support configurable polarity of level trigger interrupt
  Support configurable rising edge, falling edge and both edge trigger interrupt
  Support configurable pull direction(a weak pull-up and a weak pull-down)
  Support configurable drive strength
  Temperature Sensor (TS-ADC)
  Support User-Defined Mode and Automatic Mode
  In User-Defined Mode, start_ _of_ conversion can be controlled completely by software, and also can be generated by hardware.
  In Automatic Mode, the temperature of alarm(high/ low temperature) interrupt can be configurable
  In Automatic Mode, the temperature of system reset can be configurable
  Support to 7 channel TS-ADC, the temperature criteria of each channel can be configurable
  -40~ 125℃ temperature range and 1℃ temperature resolution

▊ Package Type

FCBGA1088L (body: 23mm x 23mm)

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▊ FET3588-C SoM, designed based on Rockchip RK3588

▊ OK3588-C development board

OK3588-C development board is to evaluate FET3588-C SoM. It leads out all functional pins of FET3588-C SoM, and makes deep optimization for different functions. Simplify user design while facilitating secondary development for users, and provide a good evaluation and design basis for your project evaluation. It supports 8K ultra-clear display, four screens with different displays, and rich high-speed data communication interfaces to meet the diverse needs of users. After rigorous testing, this product can provide stable performance support for your high-end applications.