OK3568-C Linux 5.10 Display Interface Adaptation Guide: Modifying and Debugging RGB/LVDS/MIPI/HDMI Display Parameters
1. Screen Selection
Take OK3568-C as example: The OK3568-C supports five mainstream display interfaces by default: MIPI, EDP, RGB, LVDS and HDMI,which are all pre-configured by default, and users can switch between them during the U-Boot phase.
At start-up, press Ctrl+C to enter the U-Boot command line:
Hit key to stop autoboot('CTRL+C'): 0
---------------------------------------------
0:Exit to console
1:Reboot
2:Display type
---------------------------------------------
Press 2 to enter the display type selection screen:
--------------------------------------------- hdmi==>hdmi mipi_edp==>mipi lvds_rgb=>lvds Select display 0:Exit 1:hdmi display hdmi 2:mipi_edp display mipi 3:lvds_rgb display lvds ---------------------------------------------
- 1 corresponds to the HDMI screen display
- 2 corresponds to MIPI and EDP displays; the default display is MIPI
- 3 corresponds to LVDS and RGB displays; the default display is LVDS
At this point, we can enter a number to switch the screen display; for example, we can enter 2
Writing to mmc(0)... done --------------------------------------------- hdmi==>hdmi mipi_edp==>edp lvds_rgb=>lvds Select display 0:Exit 1:hdmi display hdmi 2:mipi_edp display edp 3:lvds_rgb display lvds ---------------------------------------------
At this point, the display changes from ''mipi_edp display mipi'' to ''mipi_edp display edp'', indicating that the switch from MIPI to EDP has been completed. If you enter 2 again, you can turn off the display:
Writing to mmc(0)... done --------------------------------------------- hdmi==>hdmi mipi_edp==>off lvds_rgb=>lvds Select display 0:Exit 1:hdmi display hdmi 2:mipi_edp display off 3:lvds_rgb display lvds ---------------------------------------------
The same applies to the HDMI and LVDS_RGB options.
If you wish to retain the current settings, enter 0 to exit the screen selection menu, then enter 1 to restart.
Writing to mmc(0)... done
---------------------------------------------
hdmi==>hdmi mipi_edp==>mipi lvds_rgb=>off
Select display
0:Exit
1:hdmi display hdmi
2:mipi_edp display mipi
3:lvds_rgb display off
---------------------------------------------
/*Enter 0 exit*/ ---------------------------------------------
0:Exit to console
1:Reboot
2:Display type
---------------------------------------------
/*Press 1 to restart*/ DDR V1.18 f366f69a7d typ 23/07/17-15:48:58
In
LP4/4x derate en, other dram:2x trefi
SRX
ddrconfig:15
DDR4, 324MHz
BW=32 Col=10 Bk=4 BG=2 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
tdqss: cs0 dqs0: 120ps, dqs1: 72ps, dqs2: -48ps, dqs3: -24ps,
The configuration will take effect after a restart.
2. Adjust the screen settings
Reference Document:
User documentation source code /docs/cn/Common/DISPLAY/Rockchip_DRM_Panel_Porting_Guide
Display Parameters
Display parameter acquisition and modification
| Common Description | Device Tree Property | Meaning/Source |
| Synchronization Signals | hsync / vsync | Display parameters / Panel manual |
| Vback | hback / vback | Display parameters / Panel manual |
| Resolution | hactive / vactive | Display parameters / Panel manual |
| Vfront | hfront / vfront | Display parameters / Panel manual |
| Signal | bus-format | Display parameters / Panel manual |
| Initialisation Sequence | panel-init-sequence | Required only for MIPI screens / to be provided by the screen manufacturer |
| Clock | clock-frequency | Pixel Clock (PCLK) / Display Panel Manual |
These display parameters have corresponding entries in the device tree framework. After obtaining the parameters according to their sources, filling them into the appropriate locations completes the display setup.
Below describes the locations for entering parameters for different interfaces and important considerations when dealing with various interfaces.
2.1 RGB Interface
2.1.1 Modifying the device tree
The device tree file path corresponding to OK3568-C:
OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi
Open the device tree file, locate the ''rgb-panel'' node, and modify the display parameters in accordance with the relevant screen manual. The following are the default display parameters in the source code:
rgb-panel {
compatible = "simple-panel";
backlight = <&lvds_backlight>;
power-supply = <&vcc3v3_lcd2_n>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing1>;
timing1: timing1 {
clock-frequency = <51200000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <160>;
hback-porch = <320>;
hsync-len = <1>;
vback-porch = <35>;
vfront-porch = <12>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
Once you have modified the device tree, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilation and 6.System Flashing. (Click on the blue text to follow the link)
2.1.2 RGB Signal Format Switching:
The RGB signal formats are defined in the kernel source file ''kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c''; the available formats are RGB565, RGB666 and RGB888.
static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = {
{ DRM_MODE_CONNECTOR_Unknown, "Unknown" },
{ MEDIA_BUS_FMT_RGB565_1X16, "RGB565_1X16" },
{ MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
......
{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
......
};
The above content shows an excerpt from the code.
Once you have modified the source code, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilation and 6.System Flashing. (Click on the blue text to follow the link)
2.1.3 Viewing Screen Settings
After updating the image, you can run the following command in the command line to view the display parameters:
root@OK3568-buildroot:~# cat /sys/kernel/debug/dri/0/summary
Video Port2: ACTIVE
Connector:
DPI-1 bus_format[1011]:
RGB888_1X7X4_SPWG overlay_mode[0] output_mode[0] color_space[0], eotf:0
Display mode: 1024x600p52
clk[51200] real_clk[51200] type[48] flag[a]
H: 1024 1184 1185 1505
V: 600 612 613 648 Smart0-win0: ACTIVE
win_id: 0
format: XR24 little-endian (0x34325258) SDR[0] color_space[0] glb_alpha[0xff]
rotate: xmirror: 0 ymirror: 0 rotate_90: 0 rotate_270: 0
csc: y2r[0] r2y[0] csc mode[0]
zpos: 0
src: pos[0, 0] rect[1024 x 600]
dst: pos[0, 0] rect[1024 x 600]
buf[0]: addr: 0x000000007e2b8000 pitch: 4096 offset: 0
Connector: DPI-1: The screen node is named DPI-1;
bus_format[1011]: RGB888_1X7X4_SPWG: The RGB format uses RGB888_1X7X4_SPWG.
Display mode: 1024x600p52: Screen resolution is 1024x600;
clk[51200]: The display clock is 51.2 MHz;
Here is a specific explanation of the H and V parameters.
| H： | 1024 | 1184 | 1185 | 1505 |
| hdisplay = 1024 | hsync_start = 1184 | hsync_end = 1185 | htotal = 1505 |
hfp（Horizontal front shoulder） = hsync_start - hdisplay = 1184 - 1024 = 160 hsync（Horizontal synchronisation）= hsync_end - hsync_start = 1185 - 1184 = 1 hbp（Horizontal rear shoulder） = htotal - hsync_end = 1505 - 1185 = 320
| V： | 600 | 612 | 613 | 648 |
| vdisplay = 600 | vsync_start = 640 | vsync_end = 644 | vtotal = 684 |
vfp（Vertical front shoulder） = vsync_start - vdisplay = 640 - 600 = 40 vsync（Vertical synchronisation）= vsync_end - vsync_start = 644 - 640 = 4 vbp（Vertical rear shoulder） = vtotal - vsync_end = 684 - 644 = 40
2.1.4 RGB Interface
List of Parallel RGB Interface Formats for the RK3568
| Interface | RGB888 | RGB666 | RGB565 |
| LCDC_CLK | LCDC_CLK | LCDC_CLK | LCDC_CLK |
| LCDC_HSYNC | LCDC_HSYNC | LCDC_HSYNC | LCDC_HSYNC |
| LCDC_VSYNC | LCDC_VSYNC | LCDC_VSYNC | LCDC_VSYNC |
| LCDC_DEN | LCDC_DEN | LCDC_DEN | LCDC_DEN |
| LCDC_D23 | R7 | R5 | R4 |
| LCDC_D22 | R6 | R4 | R3 |
| LCDC_D21 | R5 | R3 | R2 |
| LCDC_D20 | R4 | R2 | R1 |
| LCDC_D19 | R3 | R1 | R0 |
| LCDC_D18 | R2 | R0 | |
| LCDC_D17 | R1 | ||
| LCDC_D16 | R0 | ||
| LCDC_D15 | G7 | G5 | G4 |
| LCDC_D14 | G6 | G4 | G3 |
| LCDC_D13 | G5 | G3 | G2 |
| LCDC_D12 | G4 | G2 | G1 |
| LCDC_D11 | G3 | G1 | G0 |
| LCDC_D10 | G2 | G0 | |
| LCDC_D9 | G1 | ||
| LCDC_D8 | G0 | ||
| LCDC_D7 | B7 | B5 | B4 |
| LCDC_D6 | B6 | B4 | B3 |
| LCDC_D5 | B5 | B3 | B2 |
| LCDC_D4 | B4 | B2 | B1 |
| LCDC_D3 | B3 | B1 | B0 |
| LCDC_D2 | B2 | B0 | |
| LCDC_D1 | B1 | ||
| LCDC_D0 | B0 |
2.2 LVDS Interface
2.2.1 Modifying the device tree
The device tree file path corresponding to OK3568-C:
OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi
Open the device tree file, locate the ''panel'' node, and modify the display parameters in accordance with the relevant screen manual. The following are the default display parameters in the source code:
panel {
compatible = "simple-panel";
backlight = <&lvds_backlight>;
power-supply = <&vcc3v3_lcd2_n>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
width-mm = <152>;
height-mm = <91>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <71000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <10>;
hfront-porch = <140>;
vback-porch = <1>;
vfront-porch = <2>;
hsync-len = <10>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
};
Once you have modified the device tree, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilationand 6.System Flashing. (Click on the blue text to follow the link)
2.2.2 LVDS Signal Format Switching:
The LVDS signal format is defined in the kernel source file ''kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c''.
static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = {
......
{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
......
{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
......
};
In the specifications, ''1X7X3'' refers to three pairs of data cables; these are generally known as screens with a ''single six'' or ''double six'' signal format;
In the specifications, ''1X7X4'' refers to four pairs of data cables; this is generally known as a screen with a ''single-eight'' or ''double-eight'' signal format.
Once you have modified the source code, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilation and 6.System Flashing. (Click on the blue text to follow the link)
2.2.3 Switching Between Single- and dual-channel LVDS Signals
Modify the &lvds node in the device tree located at kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi. By default, lvds is single-channel; adding the ''dual-channel;'' statement changes it to dual-channel:
&lvds {
dual-channel; status = "disabled";
phys = <&video_phy0>;
phy-names = "phy";
ports {
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
};
Once you have modified the device tree, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilation and 6.System Flashing.
2.2.4 Viewing Screen Settings
After updating the image, you can run the following command in the command line to view the display parameters:
root@OK3568-buildroot:~# cat /sys/kernel/debug/dri/0/summary
Video Port2: ACTIVE
Connector:
LVDS-1 bus_format[1011]:
RGB888_1X7X4_SPWG overlay_mode[0] output_mode[0] color_space[0], eotf:0
Display mode: 1280x800p60
clk[71000] real_clk[71000] type[48] flag[6]
H: 1280 1420 1430 1440
V: 800 802 822 823 Smart0-win0: ACTIVE
win_id: 0
format: XR24 little-endian (0x34325258) SDR[0] color_space[0] glb_alpha[0xff]
rotate: xmirror: 0 ymirror: 0 rotate_90: 0 rotate_270: 0
csc: y2r[0] r2y[0] csc mode[0]
zpos: 0
src: pos[0, 0] rect[1280 x 800]
dst: pos[0, 0] rect[1280 x 800]
buf[0]: addr: 0x000000007e830000 pitch: 5120 offset: 0
Connector: LVDS-1: The screen node is named LVDS-1;
bus_format[1011]: RGB888_1X7X4_SPWG: The LVDS format uses RGB888_1X7X4_SPWG.
Display mode: 1280x800p60: Screen resolution is 1280x800p60;
clk[71000]: The display clock is 71 MHz;
Here is a specific explanation of the H and V parameters.
| H： | 1280 | 1420 | 1430 | 1440 |
| hdisplay = 1280 | hsync_start = 1420 | hsync_end = 1430 | htotal = 1440 |
hfp（Horizontal front shoulder） = hsync_start - hdisplay = 1420 - 1280 = 140 hsync（Horizontal synchronisation）= hsync_end - hsync_start = 1430 - 1420 = 10 hbp（Horizontal rear shoulder） = htotal - hsync_end = 1440 - 1430 = 10
| V： | 800 | 802 | 822 | 823 |
| vdisplay = 800 | vsync_start = 802 | vsync_end = 822 | vtotal = 823 |
vfp（Vertical front shoulder） = vsync_start - vdisplay = 802 - 800 = 40 vsync（Vertical synchronisation）= vsync_end - vsync_start = 822 - 802 = 20 vbp（Vertical rear shoulder） = vtotal - vsync_end = 823 - 822 = 40
2.3 MIPI Interface
2.3.1 Modifying the device tree
The device tree file path corresponding to OK3568-C:
OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi
Open the device tree file, locate the ''& dsi1'' node, and modify the display parameters in accordance with the relevant screen manual. The following are the default display parameters in the source code:
&dsi1 {
status = "disabled";
//rockchip,lane-rate = <1000>;
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
];
panel-exit-sequence = [
];
panel-width-mm = <68>;
panel-height-mm = <121>;
backlight = <&dsi1_backlight>;
enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
display-timings {
native-mode = <&panel7_1024x600>;
panel7_1024x600: timings {
hback-porch = <40>;
hfront-porch = <40>;
hactive = <1024>;
hsync-len = <48>;
vback-porch = <40>;
vfront-porch = <40>;
vactive = <600>;
vsync-len = <4>;
clock-frequency = <43000000>;
vsync-active = <0>;
hsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
Once you have modified the device tree, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilation and 6.System Flashing. (Click on the blue text to follow the link)
2.3.2 MIPI Initialization Sequence
2.3.2.1 MIPI Initialization Sequence Acquisition
Screen manufacturers generally provide an initialization sequence for MIPI screens, similar to the example below.
We need to convert this sequence into the format reserved in Rockchip’s display subsystem.
2.3.2.2 Initialization Sequence Conversion Rules
Here is an explanation of the first sequence.
39 00 04 ff 98 81 03
| 39 | 00 | 04 | ff | 98 | 81 | 03 |
| Command type | Delay | Data Length | Command | Parameter | Parameter | Parameter |
There are the following three types of commands:
| 39 | Long Packet | Parameter > 2 |
| 15 | Short Packet | Parameter≤ 2 |
| 05 | Issue DCS commands only | Without parameters |
e.g.: 05 78 01 11
Indicates a delay of 0x78=120ms before issuing command 11.
You can achieve the effect shown in the image below using VS Code or Notepad++; the shortcut is Shift+Alt+mouse click.
2.3.3 Switching Between Single- and dual-channel MIPI Signals
Locate the &dsi1 node in the device tree at kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi
dsi,lanes = 4 A value greater than 4 for this attribute in the device tree indicates dual-channel mode for the MIPI signal; this can be modified directly to match the display’s lane requirements.
&dsi1 {
status = "disabled";
//rockchip,lane-rate = <1000>;
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
Note: During actual screen debugging, the provided screen documentation may not be entirely accurate. For example, when the screen displays abnormally (color distortion, misalignment), the normal approach is to adjust the pixel format and fine-tune the clock. Consider an alternative perspective: during initial debugging, if the screen’s clock frequency is uncertain or its range is unknown, but the display is basically functional, then the clock setting is likely approximately correct. If the screen is displaying incorrectly and adjusting the settings in the usual way does not produce a noticeable improvement, you may wish to adjust the screen’s frame rate—for example, reducing it from 60 fps to 30 fps, or to another frame rate. The main idea is to make a broad adjustment to the clock frequency.
2.4 HDMI and EDP
HDMI and eDP automatically retrieve the EDID, so there is no need to manually adjust the display settings.
2.4.1 Setting a Fixed Screen Resolution for HDMI
1. Select HDMI display during the U-Boot phase
2. Edit the driver file ''kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c'', locate the function ''dw_hdmi_connector_get_modes'', and add ''edid = NULL;''
static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
{
struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
connector);
struct hdr_static_metadata *metedata =
&connector->hdr_sink_metadata.hdmi_type1;
struct edid *edid;
struct drm_display_mode *mode;
struct drm_display_info *info = &connector->display_info;
void *data = hdmi->plat_data->phy_data;
int i, ret = 0;
memset(metedata, 0, sizeof(*metedata));
edid = dw_hdmi_get_edid(hdmi, connector);
edid = NULL; if (edid) {
int vic = 0;
dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
edid->width_cm, edid->height_cm);
drm_connector_update_edid_property(connector, edid);
cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
ret = drm_add_edid_modes(connector, edid);
if (hdmi->plat_data->get_color_changed)
hdmi->plat_data->get_yuv422_format(connector, edid);
if (hdmi->plat_data->get_colorimetry)
hdmi->plat_data->get_colorimetry(data, edid);
list_for_each_entry(mode, &connector->probed_modes, head) {
vic = drm_match_cea_mode(mode);
if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
if (vic >= 93 && vic <= 95)
mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
else if (vic == 98)
mode->picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135;
}
}
......
3. Continue editing the driver file ''kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c''. Locate the ''dw_hdmi_default_modes[]'' array, which defines a number of resolutions. Check whether it contains the resolution you require; retain only the resolution you need and comment out the rest. If the required resolution is not found in this array, you can look for it in the file ''kernel/drivers/gpu/drm/drm_edid.c'' and then add it to ''dw-hdmi.c''. Here, we will use retaining the 1280x720 resolution as an example:
static const struct drm_display_mode dw_hdmi_default_modes[] = {
/* 4 - 1280x720@60Hz 16:9 */
{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1430, 1650, 0, 720, 725, 730, 750, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, /* 16 - 1920x1080@60Hz 16:9 */
/* { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
*/ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
/* 31 - 1920x1080@50Hz 16:9 */
/* { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
*/ /* 19 - 1280x720@50Hz 16:9 */
/* { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1760, 1980, 0, 720, 725, 730, 750, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
*/ /* 17 - 720x576@50Hz 4:3 */
/* { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
796, 864, 0, 576, 581, 586, 625, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
*/ /* 2 - 720x480@60Hz 4:3 */
/* { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
798, 858, 0, 480, 489, 495, 525, 0,
DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
*/};
4. Edit the device tree file ''kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi'' and add the following timing to the ''&route_hdmi'' section:
&route_hdmi {
status = "disabled";
connect = <&vp0_out_hdmi>;
force-output;
force_timing {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <720>;
hback-porch = <220>;
hfront-porch = <110>;
vback-porch = <20>;
vfront-porch = <5>;
hsync-len = <40>;
vsync-len = <5>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <0>;
pixelclk-active = <0>;
}; };
Note: The parameters in the device tree must match those in the driver’s ''default_modes''; otherwise, the logo will not display correctly.
Once you have modified the source code, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilation and 6.System Flashing. (Click on the blue text to follow the link)
2.4.2 Setting a Fixed Screen Resolution for EDP
Refer to document: rockchip_drm_integration_helper-zh.pdf
It can be found in the following path in the source code (this was found in the source code for Linux 4.19.206):
Modify the device tree file ''kernel/arch/arm64/boot/dts/rockchip/OK3568-C-common.dtsi'' to use the ''display-timings''structure, and directly enter the EDP display’s timing parameters into the DTS file (adjust the display parameters yourself according to the display manual):
edp-panel {
compatible = "simple-panel";
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
unprepare-delay-ms = <120>;
disable-delay-ms = <120>;
backlight = <&edp_backlight>;
enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
display-timings {
native-mode = <&edp_timing1>;
edp_timing1: timing1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <160>;
hfront-porch = <136>;
vback-porch = <29>;
vfront-porch = <6>;
hsync-len = <24>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
}; port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
Once you have modified the device tree, save the configuration, recompile the kernel to generate the boot.img image, and flash the image onto the board.
For specific instructions, please refer to the 4.Related Code Compilationand 6.System Flashing. (Click on the blue text to follow the link)
After the update, when selecting the screen to display ''edp'' during the U-Boot phase, the following output can be seen:
After starting up, you can see that the screen settings have taken effect:
