OK6254-C Single Board Computer

Architecture

Up to Quad 64-bit ARM ^® Cortex ^®[email protected]

RAM

1GB/2GB DDR4-1600(regular with 1GB)

ROM

8GB eMMC

OS

Linux5.10.87+QT5.14.2

Working Voltage

DC 5V

Package

Board to board connector(4x 80-pin, 2mm combined height, 0.5mm pitch)

Dimensions

60x 38mm

Working Temperature

-40℃ ~ 85℃

OLDI/LVDS

2

– 1920x1080 @ 60fps for each display

– 1x 2048x1080 + 1x 1280x720

– OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface

24-bit RGB parallel interface

1

Camera Serial interface

1

– MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2

– Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane

Camera Serial interface

1

– MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2

– Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane

Ethernet

2

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)

– Time sensitive networking (TSN) support

– IP/UDP/TCP checksum offload in hardware

USB2.0

2

– Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

– Trace over USB supported

UART

9

– 16C750-compatible

– RS-485 external transceiver auto flow control support

– The 48 MHz functional clock is default option and allows baud rates up to 3.6 Mbps

– Stop-bit: 1, 1.5, 2 bit(s)

– Parity bit: Even, odd, none

SPI

5

– Serial clock with programmable frequency, polarity, and phase for each channel

– MCSPI Controller Clock Rates up to 50 MHz

I2C

6

– Supports a standard mode (up to 100 Kbps) and fast mode (up to 400 Kbps)

– 7-bit and 10-bit device addressing modes

McASP

3

– Transmit and Receive Clocks up to 50 MHz

– Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks

– Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats

– Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)

– Support for audio reference output clock

ePWM

3

Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:

– Two independent PWM outputs with single-edge operation

– Two independent PWM outputs with dual-edge symmetric operation

– One independent PWM output with dual-edge asymmetric operation

Dead-band generation with independent rising and falling edge delay control

eQEP

3

– Input synchronization

– Three stage/six stage digital noise filter

– Quadrature decoder unit

– Position counter and control unit for position measurement

– Quadrature edge capture unit for low-speed measurement

– Unit time base for speed and frequency measurement

– Watchdog timer for detecting stalls

– EQEP inputs (A/B/INDEX and STROBE) are available at chip level

– EQEP phase error output is also available. The status of the phase error can be observed by software through the register in the CTRL_MMR0 module.

eCAP

3

– 4 × 32 bits event time-stamp capture registers ( through )

– 4-stage sequencer (Mod4 counter), synchronized to external events (ECAPx pin edges)

– Independent edge polarity (rising / falling edge) selection for all 4 sequenced time-stamp capture events

– Input capture signal pre-scaling (from 1 to 16)

– One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events

– Continuous mode capture of time-stamps in a four-deep circular buffer

– Interrupt capabilities on any of the 4 capture events

– Absolute time-stamp capture

– Difference (Delta) mode time-stamp capture

– above resources dedicated to a single input pin

– When not used in capture mode, the ECAP module can be configured as a single channel PWM output

GPIO

n

All LVCMOS I/O can be configured as GPIO

CAN-FD

3

– Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1

– Full CAN FD support (up to 64 data bytes)

– Parity/ECC check for Message RAM

– Speed up to 5Mbps

SD

2

– 2x 4-bit SD/SDIO interface up to UHS-I

– Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0

GPMC

1

– 1× General-Purpose Memory Controller (GPMC) up to 133MHz

– Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address)
Selects (NAND, NOR, Muxed-NOR, and SRAM)

– Uses BCH Code to Support 4-, 8-, or 16-Bit ECC

– Uses Hamming Code to Support 1-Bit ECC

– Error Locator Module (ELM)
• Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials
Generated Using a BCH Algorithm
• Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms

OSPI/QSPI

1

OSPI/QSPI with 166 MHz DDR / 200MHz SDR

– Support for Serial NAND and Serial NOR flash devices

– Up to 4 CS supported

– 4GBytes memory address support

– XIP mode with optional on-the-fly encryption

Voltage input

12V

Working Temperature

-40℃ ~ 85℃

LVDS

2

Dual async channel(8 data, 2 clocks) up to 1920x1200p60, tested model: Forlinx 10.1’’ LVDS module with resolution of 1280x800 @ 60fps

16-bit RGB parallel interface

1

16-bit by FPC connector on carrier board,

Tested model: Forlinx 7’’ LCD module both resistive and capacitive TP, resolution of 1024x600@ 60fps

Camera Serial interface

1

Forlinx camera module OV5645 up to 2592X1944

Ethernet

2

10/100/1000Mbps auto-negotiation, RJ45 header

USB2.0

4

3 x USB HOST

1 x USB OTG

DEBUG UART

3

UART0 and WKUP_UART0 are converted to USB as Type-C connector on carrier board,

MCU_UART0 is available on carrier board by pin headers with pitch of 2.54mm

RS485

1

Electrical isolation

SPI

1

MCU_SPI0 by pin headers with pitch of 2.54mm, rating up to 50 MHz

I2C

2

MCU_I2C0 and WKUP_I2C0 are available on carrier board by pin headers with pitch of 2.54mm

GPMC

1

GPMC_AD0~AD15, 16-bit data and related controlling signals, by pin headers with pitch of 2.54mm

CAN-FD

1

Electrical isolation, rating up to 5Mbps

Audio

1

1x phone output and 1x MIC input

TF-CARD

1

1x TF card slot, can support UHS-I standard TF card up to 104MB/s

4G/5G

1

M.2 Key B slot for 4G and 5G which are optional and alternative,
Recommended 4G modem: Quectel EM05;
Recommend 5G modem: Quectel RM500Q;
MicroSIM slot

WiFi

1

On-board WiFi module AW-CM358M;
IEEE 802.11 a/b/g/n/ac dual-band, up to 433.3Mbps;
BT5.0, up to 3Mbps

BT

1

JTAG

1

By 2 x 10-Pin headers with pitch of 1.27mm

KEY

8

4 input keys for A core, and 1 input key for M core

LED

5

4 output LED for A core and 4 output LED for M core

RTC

1

on-board RTC chipset

EEPROM

1

2K bit, can be mounted to MCU_I2C0 or WKUP_I2C0

QSPI Flash

1

128M bit, can be mounted to QSPI or MCU_SPI0