FET-MX9352-C i.MX93 System on Module based on NXP i.MX9352 with Dual Cortex-A55 & Ethos-U65 NPU

RAM

1 GB LPDDR4

ROM

8 GB eMMC

Operating Temperature

-40 °C ~ 85 °C

Form Factor / Connectors

Board-to-board connectors (2× 100-pin connectors, 0.4 mm pitch, 1.5 mm mated height)

Dimensions

33 mm × 48 mm

OS Support

Linux 5.15.52 + Qt 6.3.2

Linux 6.1.36 + Qt 6.5.0

LVDS

1

Single 4-lane, supports 720p @ 60 fps, up to 1366 × 768 @ 60 fps or 1280 × 800 @ 60 fps

Parallel RGB

1

RGB888, up to 1366 × 768 @ 60 fps or 1280 × 800 @ 60 fps

MIPI DSI

1

1× 4-lane MIPI DSI, pixel stream from LCDIF;

Compliant with MIPI DSI v1.2 and MIPI D-PHY v1.2;

Up to 200 MHz pixel clock, 140 Mpixel/s fill rate, 24-bit RGB;

Supports 1080p @ 60 fps or 1920 × 1200 @ 60 fps, with data rate up to 1.5 Gbps per lane

Ethernet

Up to 2

Supports 2× RGMII, 1× port supports TSN;

TSN-enabled Ethernet QoS supports IEEE 802.1Qbv, IEEE 802.1Qbu, and time-based scheduling;

10/100/1000 Mbps, compliant with IEEE 802.3

uSDHC2: 4-bit, compatible with SD 3.0 and 200 MHz SDR, up to 100 MB/s;

uSDHC3: 4-bit SDIO

SAI1 supports 2 lanes, SAI2 supports 4 lanes, and SAI3 supports 1 lane;

Supports full-duplex serial audio (e.g., I2S, AC97, TDM, and Codec/DSP)

Supports raw capture mode;

Supports L-PCM and IEC61937

MIPI CSI

1

Compliant with MIPI CSI-2 v1.3 and MIPI D-PHY v1.2;

Supports up to 2× RX data lanes (and 1× RX clock lane);

Up to 200 MHz pixel clock, up to 150 Mpixel/s pixel fill rate under nominal and overdrive voltage

SPI

Up to 8

Configurable Master/Slave mode

I2C

Up to 8

Up to 100 kbit/s (Standard Mode), 400 kbit/s (Fast Mode), 1000 kbit/s (Fast Mode Plus), 3400 kbit/s (High Speed Mode), and 5000 kbit/s (Ultra Fast Mode);

Slave mode is available for High Speed Mode and Ultra Fast Mode

I3C

Up to 2

Supports 400 kbit/s (Fast Mode) and 1000 kbit/s (Fast Mode Plus), backward compatible with I2C;

Clock up to 12.5 MHz, supports HDR-DDR mode

ADC

Up to 4

1× 12-bit 4-channel, 1 MS/s ADC

JTAG

1

For Cortex-M33 debugging